(1) Field of the Invention
The present invention relates to processes used to fabricate semiconductor devices, and more specifically to a process used to create a via hole, in a dielectric layer, exposing an underlying conductive structure.
(2) Description of Prior Art
The semiconductor industry is continually striving to increase the performance of semiconductor devices, while still maintaining, or even reducing the manufacturing costs of these higher performing semiconductor devices. The ability of the industry to fabricate devices with sub-micron features, or micro-miniaturization, has allowed the performance and cost objectives to be successfully addressed. Smaller device features allow a reduction of performance degrading resistances and capacitances to be realized, resulting in performance improvements. In addition the use of sub-micron device features, allows a greater number of smaller semiconductor chips, still possessing device densities comparable to device densities obtained with larger counterparts, to be obtained from a specific size starting substrate, thus resulting in a reduction of the processing cost for a specific semiconductor chip.
The arrival of micro-miniaturization has been attributed to advances in specific semiconductor fabrication disciplines, such as photolithography and dry etching. The use of more sophisticated exposure cameras, as well as the development of more sensitive photosensitive materials, have allowed sub-micron images to be routinely formed in photoresist layers. In addition the development of more advanced dry etching tools, and processes, have allowed the sub-micron images in photoresist layers, to be successfully transferred to underlying materials, used to create advanced semiconductor devices. However in addition to advances in semiconductor fabrication disciplines, optimization of specific fabrication sequences are still needed to further reduce the manufacturing costs for semiconductor devices.
One area of semiconductor fabrication, via hole formation, has been addressed regarding cost and performance optimization. As device dimensions shrink, processes used to open sub-micron via holes in dielectric layers, become more difficult to achieve. Sub-micron images in photoresist layers, used as masks for subsequent dry etching of the sub-micron via holes, are costly process steps, and can result in unwanted damage to exposed metal surfaces, occurring from processes, and reactants, used to remove the masking photoresist shape, at the conclusion of via hole formation. This invention will describe a novel process for forming a via hole in a dielectric layer, exposing an underlying metal interconnect structure, however this invention will feature a via hole opening procedure, without the use of costly photoresist procedures. A via hole is formed in a photosensitive, low dielectric constant layer, using direct exposure, and selective removal of the exposed region. However unlike the conventional photoresist processes, the photosensitive, low dielectric constant layer is not removed, and after filling the via hole with metal, the photosensitive, low dielectric constant layer remains to function as an interlevel dielectric layer, located between underlying and overlying, metal interconnect structures. An option offered in this invention is the creation of chemically vapor deposited, insulator spacers, on the sides of the via hole, to protect the exposed sides of the photosensitive, low dielectric constant layer, from subsequent processing steps. Prior art, such as Chang et al, in U.S. Pat No. 5,559,055, describe the use of low dielectric constant materials to fill spaces between metal lines, however they do not describe the use of a photosensitive, low dielectric constant layer, used as an interlevel dielectric layer, as well as a material used for via hole formation, without the use of photosensitive photoresist materials.